1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device, a method for operating the same and a method for fabricating the same, and more particularly, to a nonvolatile memory device including a plurality of memory cells vertically stacked on a substrate, a method for operating the same and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device is a memory device that maintains stored data as is even when power supply is interrupted. Currently, various nonvolatile memory devices such as a NAND type flash memory are widely used.
As a further increase in the integration degree of a two-dimensional nonvolatile memory device in which memory cells are formed in a single layer on a silicon substrate is reaching physical limits, a three-dimensional nonvolatile memory device in which a plurality of memory cells are vertically stacked from a silicon substrate have been developed.
FIGS. 1A to 1C are views illustrating a conventional three-dimensional nonvolatile memory device, wherein FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view taken along the line A-A′ of FIG. 1A, and FIG. 1C is a plan view mainly showing word lines in FIG. 1A.
Referring to FIGS. 1A to 1C, a conventional nonvolatile memory device includes a substrate 100, channel structures C disposed on the substrate 100 and extending in a first direction (see the x axis), word lines WL_0 to WL_N extending in a second direction (see the y axis) between the channel structures C to face the sidewalls of the channel structures C, a source select line SSL and a source line SL, drain select lines DSL_0 to DSL_N disposed over the step-shaped ends of the channel structures C and extending in the second direction, and bit lines BL disposed over the drain select lines DSL_0 to DSL_N and extending in the first direction. A memory layer 130 is interposed between the word lines WL_0 to WL_N and the channel structures C, and a gate dielectric layer 140 is interposed between the source select line SSL and the channel structures C. The memory layer 130 is a layer for electrically insulating channel layers 120 and the word lines WL from each other and storing charges, where the layer may have a three-layered structure including a tunnel dielectric layer, a charge storing layer and a charge blocking layer, for example, an ONO (oxide-nitride-oxide) structure.
In detail, the channel structures C include a plurality of interlayer dielectric layers 110 and a plurality of channel layers 120, which are alternately stacked. One word line WLm, which faces one channel layer 120, and the memory layer 130 interposed between the word line WLm and the channel layer 120 constitute a unit memory cell MC. Also, the source select line SSL, which faces one channel layer 120, and the gate dielectric layer 140 interposed between the source select line SSL and the gate dielectric layer 140 constitute a source select transistor.
Channel contacts 150 are formed on the protecting ends of the respective channel layers 120, and channels 160 of drain select transistors are disposed over the respective channel contacts 150. One drain select line DSL that faces one channel 160 and a gate dielectric layer (not shown) interposed therebetween constitute a drain select transistor.
A plurality of memory cells MC that share the same channel layer 120 constitute one string ST. Accordingly, in each channel structure C, strings ST_0˜X that are stacked to have the same number as the number of the channel layers 120 are disposed. The stacked strings ST_O˜X sharing the same channel structure C are connected to the same bit line BL. Further, a plurality of stacks of strings ST_0˜X that are connected to a plurality of bit lines BL are commonly connected to one source line SL.
A plurality of memory cells MC which share the same word line WL constitute one page PAGE. Accordingly, for each word line WL, pages PAGE_0˜X are stacked to have the same number as the number of the channel layers 120. A page PAGE desired among the stacked pages PAGE_0˜X which share one word line WL may be selected by a drain select transistor.
The read and write operations of the nonvolatile memory device structured as described above may be performed, in particular, in such a way as to select desired pages PAGE using a plurality of drain select transistors while controlling the word lines WL_0 to WL_N and the bit lines BL according to a scheme generally known in the art. That is to say, in the read and write operations, desired pages PAGE may be selected by turning on drain select transistors which are connected to the desired pages PAGE and turning off the remaining drain select transistors.
However, in the above-described nonvolatile memory device, because the same word line WL faces both sidewalls of each channel layer 120, in a program or erase operation, charges are simultaneously inserted into or taken out of the charge storing layer of the memory layer 130 through both sides of a selected memory cell MC. In other words, one bit data (‘00’ or ‘11’) is stored in one memory cell MC. FIG. 1C exemplifies that data of ‘00’ is stored.
In addition, due to the structural characteristics of the above-described nonvolatile memory device, as the charge storing layer of the memory layer 130, a dielectric layer which stores charges in an energy trap, for example, a silicon nitride layer, is widely used. In this case, when compared to the charge storing layer of a floating gate type nonvolatile memory device, for example, a polysilicon layer, it is further difficult to realize a multi-level cell.
As a consequence, in the conventional three-dimensional nonvolatile memory device as described above, it is difficult to implement a multi-level cell.